module flow_led(
   input  clk,
   input  rst_n,
   output reg[2:0] led
);



reg out;
parameter    S0 = 0;
parameter    S1 =1;
parameter    S2 = 2;
parameter    S3 = 3;
reg    [3:0]    state_c;
reg    [3:0]    state_n;

wire s0_s1_start;
wire s1_s2_start;
wire s2_s3_start;


//四段式状态机
//第一段：同步时序always模块，格式化描述次态寄存器迁移到现态寄存器(不需更改）
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
    state_c <= S0;
    end
    else begin
    state_c <= state_n;
    end
end
//第二段：组合逻辑always模块，描述状态转移条件判断
always@(*)begin
    case(state_c)
        S0:begin//状态
            if(s0_s1_start)begin
                state_n = S1;//状态1
            end
            else begin
                state_n = state_c;
            end
        end

        S1:begin
            if(s1_s2_start)begin
                state_n = S2;//状态2
            end
            else begin
                state_n = state_c;
            end
        end

        S2:begin
            if(s2_s3_start)begin
                state_n = S3;//状态3
            end
            else begin
                state_n = state_c;
            end
        end
        default:begin
             state_n = S0;
        end
    endcase
end
//第三段：设计转移条件
assign s0_s1_start  = state_c==S0  && 0;
assign s1_s2_start   = state_c==S1    && 0;
assign s2_s3_start   = state_c==S2    && 0;

//第四段：同步时序always模块，格式化描述寄存器输出（可有多个输出）
always  @(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        out <=1'b0;      //初始化
    end
    else if(state_c==S1)begin
        out <= 1'b1;
    end
    else begin
        out <= 1'b0;
    end
end




endmodule
